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video_core: Use un-shifted block sizes to avoid integer divisions

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Instead of storing all block width, height and depths in their shifted
form:

block_width = 1U << block_shift;

Store them like they are provided by the emulated hardware (their
block_shift form). This way we can avoid doing the costly
Common::AlignUp operation to align texture sizes and drop CPU integer
divisions with bitwise logic (defined in Common::AlignBits).
This commit is contained in:
ReinUsesLisp
2019-05-10 04:17:48 -03:00
parent 28d7c2f5a5
commit 345e73f2fe
10 changed files with 78 additions and 60 deletions
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3
src/video_core/texture_cache/surface_base.cpp
View File

@ -22,7 +22,6 @@ SurfaceBaseImpl::SurfaceBaseImpl(GPUVAddr gpu_addr, const SurfaceParams& params)
: params{params}, mipmap_sizes(params.num_levels),
mipmap_offsets(params.num_levels), gpu_addr{gpu_addr}, host_memory_size{
params.GetHostSizeInBytes()} {
std::size_t offset = 0;
for (u32 level = 0; level < params.num_levels; ++level) {
const std::size_t mipmap_size{params.GetGuestMipmapSize(level)};
@ -75,7 +74,7 @@ void SurfaceBaseImpl::LoadBuffer(Tegra::MemoryManager& memory_manager,
return;
}
if (params.is_tiled) {
ASSERT_MSG(params.block_width == 1, "Block width is defined as {} on texture target {}",
ASSERT_MSG(params.block_width == 0, "Block width is defined as {} on texture target {}",
params.block_width, static_cast<u32>(params.target));
for (u32 level = 0; level < params.num_levels; ++level) {
const std::size_t host_offset{params.GetHostMipmapLevelOffset(level)};

39
src/video_core/texture_cache/surface_params.cpp
View File

@ -96,9 +96,9 @@ SurfaceParams SurfaceParams::CreateForDepthBuffer(
SurfaceParams params;
params.is_tiled = type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
params.srgb_conversion = false;
params.block_width = 1 << std::min(block_width, 5U);
params.block_height = 1 << std::min(block_height, 5U);
params.block_depth = 1 << std::min(block_depth, 5U);
params.block_width = std::min(block_width, 5U);
params.block_height = std::min(block_height, 5U);
params.block_depth = std::min(block_depth, 5U);
params.tile_width_spacing = 1;
params.pixel_format = PixelFormatFromDepthFormat(format);
params.component_type = ComponentTypeFromDepthFormat(format);
@ -120,9 +120,9 @@ SurfaceParams SurfaceParams::CreateForFramebuffer(Core::System& system, std::siz
config.memory_layout.type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
params.srgb_conversion = config.format == Tegra::RenderTargetFormat::BGRA8_SRGB ||
config.format == Tegra::RenderTargetFormat::RGBA8_SRGB;
params.block_width = 1 << config.memory_layout.block_width;
params.block_height = 1 << config.memory_layout.block_height;
params.block_depth = 1 << config.memory_layout.block_depth;
params.block_width = config.memory_layout.block_width;
params.block_height = config.memory_layout.block_height;
params.block_depth = config.memory_layout.block_depth;
params.tile_width_spacing = 1;
params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
params.component_type = ComponentTypeFromRenderTarget(config.format);
@ -149,9 +149,9 @@ SurfaceParams SurfaceParams::CreateForFermiCopySurface(
params.is_tiled = !config.linear;
params.srgb_conversion = config.format == Tegra::RenderTargetFormat::BGRA8_SRGB ||
config.format == Tegra::RenderTargetFormat::RGBA8_SRGB;
params.block_width = params.is_tiled ? std::min(config.BlockWidth(), 32U) : 0,
params.block_height = params.is_tiled ? std::min(config.BlockHeight(), 32U) : 0,
params.block_depth = params.is_tiled ? std::min(config.BlockDepth(), 32U) : 0,
params.block_width = params.is_tiled ? std::min(config.BlockWidth(), 5U) : 0,
params.block_height = params.is_tiled ? std::min(config.BlockHeight(), 5U) : 0,
params.block_depth = params.is_tiled ? std::min(config.BlockDepth(), 5U) : 0,
params.tile_width_spacing = 1;
params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
params.component_type = ComponentTypeFromRenderTarget(config.format);
@ -190,9 +190,9 @@ u32 SurfaceParams::GetMipBlockHeight(u32 level) const {
const u32 height{GetMipHeight(level)};
const u32 default_block_height{GetDefaultBlockHeight()};
const u32 blocks_in_y{(height + default_block_height - 1) / default_block_height};
u32 block_height = 16;
while (block_height > 1 && blocks_in_y <= block_height * 4) {
block_height >>= 1;
u32 block_height = 4;
while (block_height > 0 && blocks_in_y <= (1U << block_height) * 4) {
--block_height;
}
return block_height;
}
@ -202,17 +202,17 @@ u32 SurfaceParams::GetMipBlockDepth(u32 level) const {
return this->block_depth;
}
if (is_layered) {
return 1;
return 0;
}
const u32 depth{GetMipDepth(level)};
u32 block_depth = 32;
while (block_depth > 1 && depth * 2 <= block_depth) {
block_depth >>= 1;
u32 block_depth = 5;
while (block_depth > 0 && depth * 2 <= (1U << block_depth)) {
--block_depth;
}
if (block_depth == 32 && GetMipBlockHeight(level) >= 4) {
return 16;
if (block_depth == 5 && GetMipBlockHeight(level) >= 2) {
return 4;
}
return block_depth;
@ -252,7 +252,8 @@ std::size_t SurfaceParams::GetLayerSize(bool as_host_size, bool uncompressed) co
size += GetInnerMipmapMemorySize(level, as_host_size, uncompressed);
}
if (is_tiled && is_layered) {
return Common::AlignUp(size, Tegra::Texture::GetGOBSize() * block_height * block_depth);
return Common::AlignBits(size,
Tegra::Texture::GetGOBSizeShift() + block_height + block_depth);
}
return size;
}

7
src/video_core/texture_cache/surface_params.h
View File

@ -54,12 +54,12 @@ public:
constexpr std::size_t rgb8_bpp = 4ULL;
// ASTC is uncompressed in software, in emulated as RGBA8
host_size_in_bytes = 0;
for (std::size_t level = 0; level < num_levels; level++) {
for (u32 level = 0; level < num_levels; ++level) {
const std::size_t width =
Common::AlignUp(GetMipWidth(level), GetDefaultBlockWidth());
const std::size_t height =
Common::AlignUp(GetMipHeight(level), GetDefaultBlockHeight());
const std::size_t depth = is_layered ? depth : GetMipDepth(level);
const std::size_t depth = is_layered ? this->depth : GetMipDepth(level);
host_size_in_bytes += width * height * depth * rgb8_bpp;
}
} else {
@ -96,7 +96,8 @@ public:
// Helper used for out of class size calculations
static std::size_t AlignLayered(const std::size_t out_size, const u32 block_height,
const u32 block_depth) {
return Common::AlignUp(out_size, Tegra::Texture::GetGOBSize() * block_height * block_depth);
return Common::AlignBits(out_size,
Tegra::Texture::GetGOBSizeShift() + block_height + block_depth);
}
/// Returns the offset in bytes in guest memory of a given mipmap level.

3
src/video_core/texture_cache/texture_cache.h
View File

@ -81,6 +81,9 @@ public:
if (!gpu_addr) {
return {};
}
if (gpu_addr == 0x1b7ec0000) {
// __debugbreak();
}
const auto params{SurfaceParams::CreateForTexture(system, config, entry)};
return GetSurface(gpu_addr, params, true).second;
}