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shader: Reimplement GetCbufU64 as GetCbufU32x2

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It may generate better code on some compilers and it's easier to handle.
This commit is contained in:
ReinUsesLisp
2021-04-04 02:31:09 -03:00
committed by ameerj
parent 5b3c6d59c2
commit 3f594dd86b
9 changed files with 21 additions and 22 deletions
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6
src/shader_recompiler/frontend/ir/ir_emitter.cpp
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@ -162,8 +162,8 @@ U32 IREmitter::GetCbuf(const U32& binding, const U32& byte_offset) {
return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset);
}
UAny IREmitter::GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
bool is_signed) {
Value IREmitter::GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
bool is_signed) {
switch (bitsize) {
case 8:
return Inst<U32>(is_signed ? Opcode::GetCbufS8 : Opcode::GetCbufU8, binding, byte_offset);
@ -172,7 +172,7 @@ UAny IREmitter::GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsi
case 32:
return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset);
case 64:
return Inst<U64>(Opcode::GetCbufU64, binding, byte_offset);
return Inst(Opcode::GetCbufU32x2, binding, byte_offset);
default:
throw InvalidArgument("Invalid bit size {}", bitsize);
}

4
src/shader_recompiler/frontend/ir/ir_emitter.h
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@ -56,8 +56,8 @@ public:
void SetIndirectBranchVariable(const U32& value);
[[nodiscard]] U32 GetCbuf(const U32& binding, const U32& byte_offset);
[[nodiscard]] UAny GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
bool is_signed);
[[nodiscard]] Value GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
bool is_signed);
[[nodiscard]] F32 GetFloatCbuf(const U32& binding, const U32& byte_offset);
[[nodiscard]] U1 GetZFlag();

2
src/shader_recompiler/frontend/ir/opcodes.inc
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@ -40,7 +40,7 @@ OPCODE(GetCbufU16, U32, U32,
OPCODE(GetCbufS16, U32, U32, U32, )
OPCODE(GetCbufU32, U32, U32, U32, )
OPCODE(GetCbufF32, F32, U32, U32, )
OPCODE(GetCbufU64, U64, U32, U32, )
OPCODE(GetCbufU32x2, U32x2, U32, U32, )
OPCODE(GetAttribute, F32, Attribute, )
OPCODE(SetAttribute, Void, Attribute, F32, )
OPCODE(GetAttributeIndexed, F32, U32, )

12
src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp
View File

@ -30,25 +30,25 @@ void TranslatorVisitor::LDC(u64 insn) {
const auto [index, offset]{Slot(ir, ldc.mode, imm_index, reg, imm)};
switch (ldc.size) {
case Size::U8:
X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, false));
X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 8, false)});
break;
case Size::S8:
X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, true));
X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 8, true)});
break;
case Size::U16:
X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, false));
X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 16, false)});
break;
case Size::S16:
X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, true));
X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 16, true)});
break;
case Size::B32:
X(ldc.dest_reg, ir.GetCbuf(index, offset, 32, false));
X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 32, false)});
break;
case Size::B64: {
if (!IR::IsAligned(ldc.dest_reg, 2)) {
throw NotImplementedException("Unaligned destination register");
}
const IR::Value vector{ir.UnpackUint2x32(ir.GetCbuf(index, offset, 64, false))};
const IR::Value vector{ir.GetCbuf(index, offset, 64, false)};
for (int i = 0; i < 2; ++i) {
X(ldc.dest_reg + i, IR::U32{ir.CompositeExtract(vector, i)});
}