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Merge pull request #9556 from vonchenplus/draw_texture
video_core: Implement maxwell3d draw texture method
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@ -51,6 +51,10 @@ void DrawManager::ProcessMethodCall(u32 method, u32 argument) {
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LOG_WARNING(HW_GPU, "(STUBBED) called");
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break;
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}
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case MAXWELL3D_REG_INDEX(draw_texture.src_y0): {
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DrawTexture();
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break;
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}
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default:
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break;
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}
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@ -179,6 +183,33 @@ void DrawManager::DrawIndexSmall(u32 argument) {
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ProcessDraw(true, 1);
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}
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void DrawManager::DrawTexture() {
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const auto& regs{maxwell3d->regs};
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draw_texture_state.dst_x0 = static_cast<float>(regs.draw_texture.dst_x0) / 4096.f;
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draw_texture_state.dst_y0 = static_cast<float>(regs.draw_texture.dst_y0) / 4096.f;
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const auto dst_width = static_cast<float>(regs.draw_texture.dst_width) / 4096.f;
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const auto dst_height = static_cast<float>(regs.draw_texture.dst_height) / 4096.f;
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const bool lower_left{regs.window_origin.mode !=
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Maxwell3D::Regs::WindowOrigin::Mode::UpperLeft};
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if (lower_left) {
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draw_texture_state.dst_y0 -= dst_height;
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}
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draw_texture_state.dst_x1 = draw_texture_state.dst_x0 + dst_width;
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draw_texture_state.dst_y1 = draw_texture_state.dst_y0 + dst_height;
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draw_texture_state.src_x0 = static_cast<float>(regs.draw_texture.src_x0) / 4096.f;
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draw_texture_state.src_y0 = static_cast<float>(regs.draw_texture.src_y0) / 4096.f;
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draw_texture_state.src_x1 =
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(static_cast<float>(regs.draw_texture.dx_du) / 4294967296.f) * dst_width +
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draw_texture_state.src_x0;
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draw_texture_state.src_y1 =
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(static_cast<float>(regs.draw_texture.dy_dv) / 4294967296.f) * dst_height +
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draw_texture_state.src_y0;
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draw_texture_state.src_sampler = regs.draw_texture.src_sampler;
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draw_texture_state.src_texture = regs.draw_texture.src_texture;
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maxwell3d->rasterizer->DrawTexture();
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}
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void DrawManager::UpdateTopology() {
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const auto& regs{maxwell3d->regs};
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switch (regs.primitive_topology_control) {
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@ -32,6 +32,19 @@ public:
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std::vector<u8> inline_index_draw_indexes;
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};
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struct DrawTextureState {
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f32 dst_x0;
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f32 dst_y0;
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f32 dst_x1;
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f32 dst_y1;
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f32 src_x0;
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f32 src_y0;
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f32 src_x1;
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f32 src_y1;
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u32 src_sampler;
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u32 src_texture;
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};
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struct IndirectParams {
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bool is_indexed;
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bool include_count;
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@ -64,6 +77,10 @@ public:
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return draw_state;
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}
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const DrawTextureState& GetDrawTextureState() const {
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return draw_texture_state;
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}
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IndirectParams& GetIndirectParams() {
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return indirect_state;
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}
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@ -81,6 +98,8 @@ private:
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void DrawIndexSmall(u32 argument);
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void DrawTexture();
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void UpdateTopology();
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void ProcessDraw(bool draw_indexed, u32 instance_count);
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@ -89,6 +108,7 @@ private:
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Maxwell3D* maxwell3d{};
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State draw_state{};
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DrawTextureState draw_texture_state{};
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IndirectParams indirect_state{};
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};
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} // namespace Tegra::Engines
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@ -149,6 +149,7 @@ bool Maxwell3D::IsMethodExecutable(u32 method) {
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case MAXWELL3D_REG_INDEX(inline_index_4x8.index0):
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case MAXWELL3D_REG_INDEX(vertex_array_instance_first):
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case MAXWELL3D_REG_INDEX(vertex_array_instance_subsequent):
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case MAXWELL3D_REG_INDEX(draw_texture.src_y0):
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case MAXWELL3D_REG_INDEX(wait_for_idle):
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case MAXWELL3D_REG_INDEX(shadow_ram_control):
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case MAXWELL3D_REG_INDEX(load_mme.instruction_ptr):
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@ -1599,6 +1599,20 @@ public:
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};
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static_assert(sizeof(TIRModulationCoeff) == 0x4);
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struct DrawTexture {
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s32 dst_x0;
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s32 dst_y0;
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s32 dst_width;
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s32 dst_height;
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s64 dx_du;
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s64 dy_dv;
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u32 src_sampler;
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u32 src_texture;
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s32 src_x0;
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s32 src_y0;
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};
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static_assert(sizeof(DrawTexture) == 0x30);
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struct ReduceColorThreshold {
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union {
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BitField<0, 8, u32> all_hit_once;
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@ -2751,7 +2765,7 @@ public:
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u32 reserved_sw_method2; ///< 0x102C
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std::array<TIRModulationCoeff, 5> tir_modulation_coeff; ///< 0x1030
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std::array<u32, 15> spare_nop; ///< 0x1044
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INSERT_PADDING_BYTES_NOINIT(0x30);
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DrawTexture draw_texture; ///< 0x1080
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std::array<u32, 7> reserved_sw_method3_to_7; ///< 0x10B0
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ReduceColorThreshold reduce_color_thresholds_unorm8; ///< 0x10CC
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std::array<u32, 4> reserved_sw_method10_to_13; ///< 0x10D0
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