mirror of
https://github.com/yuzu-emu/yuzu-android.git
synced 2025-06-26 18:37:55 -05:00
got rid of 'src' folders in each sub-project
This commit is contained in:
bunnei
1132
src/core/arm/mmu/arm1176jzf_s_mmu.cpp
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1132
src/core/arm/mmu/arm1176jzf_s_mmu.cpp
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File diff suppressed because it is too large
Load Diff
37
src/core/arm/mmu/arm1176jzf_s_mmu.h
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37
src/core/arm/mmu/arm1176jzf_s_mmu.h
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/*
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arm1176JZF-S_mmu.h - ARM1176JZF-S Memory Management Unit emulation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ARM1176JZF_S_MMU_H_
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#define _ARM1176JZF_S_MMU_H_
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#if 0
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typedef struct arm1176jzf-s_mmu_s
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{
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tlb_t i_tlb;
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cache_t i_cache;
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tlb_t d_tlb;
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cache_t d_cache;
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wb_t wb_t;
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} arm1176jzf-s_mmu_t;
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#endif
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extern mmu_ops_t arm1176jzf_s_mmu_ops;
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ARMword
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arm1176jzf_s_mmu_mrc (ARMul_State *state, ARMword instr, ARMword *value);
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#endif /*_ARM1176JZF_S_MMU_H_*/
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168
src/core/arm/mmu/cache.h
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168
src/core/arm/mmu/cache.h
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@ -0,0 +1,168 @@
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#ifndef _MMU_CACHE_H_
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#define _MMU_CACHE_H_
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typedef struct cache_line_t
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{
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ARMword tag; /* cache line align address |
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bit2: last half dirty
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bit1: first half dirty
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bit0: cache valid flag
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*/
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ARMword pa; /*physical address */
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ARMword *data; /*array of cached data */
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} cache_line_t;
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#define TAG_VALID_FLAG 0x00000001
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#define TAG_FIRST_HALF_DIRTY 0x00000002
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#define TAG_LAST_HALF_DIRTY 0x00000004
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/*cache set association*/
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typedef struct cache_set_s
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{
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cache_line_t *lines;
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int cycle;
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} cache_set_t;
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enum
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{
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CACHE_WRITE_BACK,
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CACHE_WRITE_THROUGH,
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};
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typedef struct cache_s
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{
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int width; /*bytes in a line */
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int way; /*way of set asscociate */
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int set; /*num of set */
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int w_mode; /*write back or write through */
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//int a_mode; /*alloc mode: random or round-bin*/
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cache_set_t *sets;
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/**/} cache_s;
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typedef struct cache_desc_s
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{
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int width;
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int way;
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int set;
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int w_mode;
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// int a_mode;
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} cache_desc_t;
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/*virtual address to cache set index*/
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#define va_cache_set(va, cache_t) \
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(((va) / (cache_t)->width) & ((cache_t)->set - 1))
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/*virtual address to cahce line aligned*/
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#define va_cache_align(va, cache_t) \
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((va) & ~((cache_t)->width - 1))
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/*virtaul address to cache line word index*/
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#define va_cache_index(va, cache_t) \
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(((va) & ((cache_t)->width - 1)) >> WORD_SHT)
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/*see Page 558 in arm manual*/
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/*set/index format value to cache set value*/
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#define index_cache_set(index, cache_t) \
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(((index) / (cache_t)->width) & ((cache_t)->set - 1))
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/*************************cache********************/
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/* mmu cache init
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*
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* @cache_t :cache_t to init
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* @width :cache line width in byte
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* @way :way of each cache set
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* @set :cache set num
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* @w_mode :cache w_mode
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*
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* $ -1: error
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* 0: sucess
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*/
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int
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mmu_cache_init (cache_s * cache_t, int width, int way, int set, int w_mode);
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/* free a cache_t's inner data, the ptr self is not freed,
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* when needed do like below:
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* mmu_cache_exit(cache);
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* free(cache_t);
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*
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* @cache_t : the cache_t to free
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*/
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void mmu_cache_exit (cache_s * cache_t);
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/* mmu cache search
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*
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* @state :ARMul_State
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* @cache_t :cache_t to search
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* @va :virtual address
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*
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* $ NULL: no cache match
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* cache :cache matched
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* */
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cache_line_t *mmu_cache_search (ARMul_State * state, cache_s * cache_t,
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ARMword va);
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/* mmu cache search by set/index
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*
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* @state :ARMul_State
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* @cache_t :cache_t to search
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* @index :set/index value.
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*
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* $ NULL: no cache match
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* cache :cache matched
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* */
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cache_line_t *mmu_cache_search_by_index (ARMul_State * state,
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cache_s * cache_t, ARMword index);
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/* mmu cache alloc
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*
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* @state :ARMul_State
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* @cache_t :cache_t to alloc from
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* @va :virtual address that require cache alloc, need not cache aligned
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* @pa :physical address of va
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*
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* $ cache_alloced, always alloc OK
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*/
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cache_line_t *mmu_cache_alloc (ARMul_State * state, cache_s * cache_t,
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ARMword va, ARMword pa);
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/* mmu_cache_write_back write cache data to memory
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*
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* @state:
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* @cache_t :cache_t of the cache line
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* @cache : cache line
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*/
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void
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mmu_cache_write_back (ARMul_State * state, cache_s * cache_t,
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cache_line_t * cache);
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/* mmu_cache_clean: clean a cache of va in cache_t
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*
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* @state :ARMul_State
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* @cache_t :cache_t to clean
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* @va :virtaul address
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*/
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void mmu_cache_clean (ARMul_State * state, cache_s * cache_t, ARMword va);
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void
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mmu_cache_clean_by_index (ARMul_State * state, cache_s * cache_t,
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ARMword index);
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/* mmu_cache_invalidate : invalidate a cache of va
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*
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* @state :ARMul_State
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* @cache_t :cache_t to invalid
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* @va :virt_addr to invalid
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*/
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void
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mmu_cache_invalidate (ARMul_State * state, cache_s * cache_t, ARMword va);
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void
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mmu_cache_invalidate_by_index (ARMul_State * state, cache_s * cache_t,
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ARMword index);
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void mmu_cache_invalidate_all (ARMul_State * state, cache_s * cache_t);
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void
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mmu_cache_soft_flush (ARMul_State * state, cache_s * cache_t, ARMword pa);
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cache_line_t* mmu_cache_dirty_cache(ARMul_State * state, cache_s * cache_t);
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#endif /*_MMU_CACHE_H_*/
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55
src/core/arm/mmu/rb.h
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55
src/core/arm/mmu/rb.h
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@ -0,0 +1,55 @@
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#ifndef _MMU_RB_H
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#define _MMU_RB_H
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enum rb_type_t
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{
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RB_INVALID = 0, //invalid
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RB_1, //1 word
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RB_4, //4 word
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RB_8, //8 word
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};
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/*bytes of each rb_type*/
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extern ARMword rb_masks[];
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#define RB_WORD_NUM 8
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typedef struct rb_entry_s
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{
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ARMword data[RB_WORD_NUM]; //array to store data
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ARMword va; //first word va
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int type; //rb type
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fault_t fault; //fault set by rb alloc
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} rb_entry_t;
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typedef struct rb_s
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{
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int num;
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rb_entry_t *entrys;
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} rb_s;
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/*mmu_rb_init
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* @rb_t :rb_t to init
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* @num :number of entry
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* */
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int mmu_rb_init (rb_s * rb_t, int num);
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/*mmu_rb_exit*/
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void mmu_rb_exit (rb_s * rb_t);
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/*mmu_rb_search
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* @rb_t :rb_t to serach
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* @va :va address to math
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*
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* $ NULL :not match
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* NO-NULL:
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* */
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rb_entry_t *mmu_rb_search (rb_s * rb_t, ARMword va);
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void mmu_rb_invalidate_entry (rb_s * rb_t, int i);
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void mmu_rb_invalidate_all (rb_s * rb_t);
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void mmu_rb_load (ARMul_State * state, rb_s * rb_t, int i_rb,
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int type, ARMword va);
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#endif /*_MMU_RB_H_*/
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94
src/core/arm/mmu/tlb.h
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94
src/core/arm/mmu/tlb.h
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@ -0,0 +1,94 @@
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#ifndef _MMU_TLB_H_
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#define _MMU_TLB_H_
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typedef enum tlb_mapping_t
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{
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TLB_INVALID = 0,
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TLB_SMALLPAGE = 1,
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TLB_LARGEPAGE = 2,
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TLB_SECTION = 3,
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TLB_ESMALLPAGE = 4,
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TLB_TINYPAGE = 5
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} tlb_mapping_t;
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extern ARMword tlb_masks[];
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/* Permissions bits in a TLB entry:
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*
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* 31 12 11 10 9 8 7 6 5 4 3 2 1 0
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* +-------------+-----+-----+-----+-----+---+---+-------+
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* Page:| | ap3 | ap2 | ap1 | ap0 | C | B | |
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* +-------------+-----+-----+-----+-----+---+---+-------+
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*
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* 31 12 11 10 9 4 3 2 1 0
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* +-------------+-----+-----------------+---+---+-------+
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* Section: | | AP | | C | B | |
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* +-------------+-----+-----------------+---+---+-------+
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*/
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/*
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section:
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section base address [31:20]
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AP - table 8-2, page 8-8
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domain
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C,B
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page:
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page base address [31:16] or [31:12]
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ap[3:0]
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domain (from L1)
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C,B
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*/
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typedef struct tlb_entry_t
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{
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ARMword virt_addr;
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ARMword phys_addr;
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ARMword perms;
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ARMword domain;
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tlb_mapping_t mapping;
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} tlb_entry_t;
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typedef struct tlb_s
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{
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int num; /*num of tlb entry */
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int cycle; /*current tlb cycle */
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tlb_entry_t *entrys;
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} tlb_s;
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#define tlb_c_flag(tlb) \
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((tlb)->perms & 0x8)
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#define tlb_b_flag(tlb) \
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((tlb)->perms & 0x4)
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#define tlb_va_to_pa(tlb, va) \
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(\
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{\
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ARMword mask = tlb_masks[tlb->mapping]; \
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(tlb->phys_addr & mask) | (va & ~mask);\
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}\
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)
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fault_t
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check_access (ARMul_State * state, ARMword virt_addr, tlb_entry_t * tlb,
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int read);
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fault_t
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translate (ARMul_State * state, ARMword virt_addr, tlb_s * tlb_t,
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tlb_entry_t ** tlb);
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int mmu_tlb_init (tlb_s * tlb_t, int num);
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void mmu_tlb_exit (tlb_s * tlb_t);
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void mmu_tlb_invalidate_all (ARMul_State * state, tlb_s * tlb_t);
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void
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mmu_tlb_invalidate_entry (ARMul_State * state, tlb_s * tlb_t, ARMword addr);
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tlb_entry_t *mmu_tlb_search (ARMul_State * state, tlb_s * tlb_t,
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ARMword virt_addr);
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#endif /*_MMU_TLB_H_*/
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63
src/core/arm/mmu/wb.h
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63
src/core/arm/mmu/wb.h
Normal file
@ -0,0 +1,63 @@
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#ifndef _MMU_WB_H_
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#define _MMU_WB_H_
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typedef struct wb_entry_s
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{
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ARMword pa; //phy_addr
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ARMbyte *data; //data
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int nb; //number byte to write
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} wb_entry_t;
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typedef struct wb_s
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{
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int num; //number of wb_entry
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int nb; //number of byte of each entry
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int first; //
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int last; //
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int used; //
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wb_entry_t *entrys;
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} wb_s;
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typedef struct wb_desc_s
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{
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int num;
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int nb;
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} wb_desc_t;
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/* wb_init
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* @wb_t :wb_t to init
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* @num :num of entrys
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* @nw :num of word of each entry
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*
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* $ -1:error
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* 0:ok
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* */
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int mmu_wb_init (wb_s * wb_t, int num, int nb);
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/* wb_exit
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* @wb_t :wb_t to exit
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* */
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void mmu_wb_exit (wb_s * wb);
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/* wb_write_bytes :put bytess in Write Buffer
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* @state: ARMul_State
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* @wb_t: write buffer
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* @pa: physical address
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* @data: data ptr
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* @n number of byte to write
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*
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* Note: write buffer merge is not implemented, can be done late
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* */
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void
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mmu_wb_write_bytess (ARMul_State * state, wb_s * wb_t, ARMword pa,
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ARMbyte * data, int n);
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/* wb_drain_all
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* @wb_t wb_t to drain
|
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* */
|
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void mmu_wb_drain_all (ARMul_State * state, wb_s * wb_t);
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#endif /*_MMU_WB_H_*/
|
||||
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