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shader: SSA and dominance

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This commit is contained in:
ReinUsesLisp
2021-02-02 21:07:00 -03:00
committed by ameerj
parent 2d48a7b4d0
commit 6c4cc0cd06
24 changed files with 569 additions and 76 deletions
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9
src/shader_recompiler/frontend/ir/reg.h
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@ -271,6 +271,9 @@ enum class Reg : u64 {
};
static_assert(static_cast<int>(Reg::RZ) == 255);
constexpr size_t NUM_USER_REGS = 255;
constexpr size_t NUM_REGS = 256;
[[nodiscard]] constexpr Reg operator+(Reg reg, int num) {
if (reg == Reg::RZ) {
// Adding or subtracting registers from RZ yields RZ
@ -290,8 +293,12 @@ static_assert(static_cast<int>(Reg::RZ) == 255);
return reg + (-num);
}
[[nodiscard]] constexpr size_t RegIndex(Reg reg) noexcept {
return static_cast<size_t>(reg);
}
[[nodiscard]] constexpr bool IsAligned(Reg reg, size_t align) {
return (static_cast<size_t>(reg) / align) * align == static_cast<size_t>(reg);
return (RegIndex(reg) / align) * align == RegIndex(reg);
}
} // namespace Shader::IR