mirror of
https://github.com/yuzu-emu/yuzu-android.git
synced 2025-06-13 08:49:02 -05:00
Make a GPU class in VideoCore to contain the GPU state.
Also moved the GPU MemoryManager class to video_core since it makes more sense for it to be there.
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@ -16,30 +16,18 @@
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/maxwell_compute.h"
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#include "video_core/gpu.h"
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#include "video_core/renderer_base.h"
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#include "video_core/video_core.h"
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namespace Tegra {
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namespace CommandProcessor {
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enum class BufferMethods {
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BindObject = 0,
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CountBufferMethods = 0x100,
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};
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enum class EngineID {
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FERMI_TWOD_A = 0x902D, // 2D Engine
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MAXWELL_B = 0xB197, // 3D Engine
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MAXWELL_COMPUTE_B = 0xB1C0,
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KEPLER_INLINE_TO_MEMORY_B = 0xA140,
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MAXWELL_DMA_COPY_A = 0xB0B5,
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};
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// Mapping of subchannels to their bound engine ids.
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static std::unordered_map<u32, EngineID> bound_engines;
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static void WriteReg(u32 method, u32 subchannel, u32 value) {
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void GPU::WriteReg(u32 method, u32 subchannel, u32 value) {
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LOG_WARNING(HW_GPU, "Processing method %08X on subchannel %u value %08X", method, subchannel,
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value);
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@ -63,22 +51,25 @@ static void WriteReg(u32 method, u32 subchannel, u32 value) {
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switch (engine) {
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case EngineID::FERMI_TWOD_A:
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Engines::Fermi2D::WriteReg(method, value);
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fermi_2d->WriteReg(method, value);
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break;
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case EngineID::MAXWELL_B:
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Engines::Maxwell3D::WriteReg(method, value);
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maxwell_3d->WriteReg(method, value);
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break;
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case EngineID::MAXWELL_COMPUTE_B:
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Engines::MaxwellCompute::WriteReg(method, value);
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maxwell_compute->WriteReg(method, value);
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break;
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default:
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UNIMPLEMENTED();
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}
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}
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void ProcessCommandList(VAddr address, u32 size) {
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VAddr current_addr = address;
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while (current_addr < address + size * sizeof(CommandHeader)) {
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void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
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// TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an
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// application VAddr.
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const VAddr head_address = memory_manager->PhysicalToVirtualAddress(address);
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VAddr current_addr = head_address;
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while (current_addr < head_address + size * sizeof(CommandHeader)) {
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const CommandHeader header = {Memory::Read32(current_addr)};
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current_addr += sizeof(u32);
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@ -125,6 +116,4 @@ void ProcessCommandList(VAddr address, u32 size) {
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}
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}
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} // namespace CommandProcessor
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} // namespace Tegra
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