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GPU: Partially implemented the QUERY_* registers in the Maxwell3D engine.

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Only QueryMode::Write is supported at the moment.
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Subv
2018-02-12 12:34:41 -05:00
parent 6cddf9d88e
commit ac61a7d1e6
3 changed files with 95 additions and 3 deletions
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40
src/video_core/engines/maxwell_3d.cpp
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@ -2,12 +2,50 @@
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/assert.h"
#include "video_core/engines/maxwell_3d.h"
namespace Tegra {
namespace Engines {
void Maxwell3D::WriteReg(u32 method, u32 value) {}
Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
void Maxwell3D::WriteReg(u32 method, u32 value) {
ASSERT_MSG(method < Regs::NUM_REGS,
"Invalid Maxwell3D register, increase the size of the Regs structure");
regs.reg_array[method] = value;
#define MAXWELL3D_REG_INDEX(field_name) (offsetof(Regs, field_name) / sizeof(u32))
switch (method) {
case MAXWELL3D_REG_INDEX(query.query_get): {
ProcessQueryGet();
break;
}
default:
break;
}
#undef MAXWELL3D_REG_INDEX
}
void Maxwell3D::ProcessQueryGet() {
GPUVAddr sequence_address = regs.query.QueryAddress();
// Since the sequence address is given as a GPU VAddr, we have to convert it to an application
// VAddr before writing.
VAddr address = memory_manager.PhysicalToVirtualAddress(sequence_address);
switch (regs.query.query_get.mode) {
case Regs::QueryMode::Write: {
// Write the current query sequence to the sequence address.
u32 sequence = regs.query.query_sequence;
Memory::Write32(address, sequence);
break;
}
default:
UNIMPLEMENTED_MSG("Query mode %u not implemented", regs.query.query_get.mode.Value());
}
}
} // namespace Engines
} // namespace Tegra