Merge pull request #178 from Subv/command_buffers

GPU: Added a command processor to decode the GPU pushbuffers and forward the commands to their respective engines

src/video_core/CMakeLists.txt

@@ -1,4 +1,15 @@
 add_library(video_core STATIC
+    command_processor.cpp
+    command_processor.h
+    engines/fermi_2d.cpp
+    engines/fermi_2d.h
+    engines/maxwell_3d.cpp
+    engines/maxwell_3d.h
+    engines/maxwell_compute.cpp
+    engines/maxwell_compute.h
+    gpu.h
+    memory_manager.cpp
+    memory_manager.h
     renderer_base.cpp
     renderer_base.h
     renderer_opengl/gl_resource_manager.h

src/video_core/command_processor.cpp

@@ -0,0 +1,119 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include <array>
+#include <cstddef>
+#include <memory>
+#include <utility>
+#include "common/assert.h"
+#include "common/logging/log.h"
+#include "common/microprofile.h"
+#include "common/vector_math.h"
+#include "core/memory.h"
+#include "core/tracer/recorder.h"
+#include "video_core/command_processor.h"
+#include "video_core/engines/fermi_2d.h"
+#include "video_core/engines/maxwell_3d.h"
+#include "video_core/engines/maxwell_compute.h"
+#include "video_core/gpu.h"
+#include "video_core/renderer_base.h"
+#include "video_core/video_core.h"
+
+namespace Tegra {
+
+enum class BufferMethods {
+    BindObject = 0,
+    CountBufferMethods = 0x100,
+};
+
+void GPU::WriteReg(u32 method, u32 subchannel, u32 value) {
+    LOG_WARNING(HW_GPU, "Processing method %08X on subchannel %u value %08X", method, subchannel,
+                value);
+
+    if (method == static_cast<u32>(BufferMethods::BindObject)) {
+        // Bind the current subchannel to the desired engine id.
+        LOG_DEBUG(HW_GPU, "Binding subchannel %u to engine %u", subchannel, value);
+        ASSERT(bound_engines.find(subchannel) == bound_engines.end());
+        bound_engines[subchannel] = static_cast<EngineID>(value);
+        return;
+    }
+
+    if (method < static_cast<u32>(BufferMethods::CountBufferMethods)) {
+        // TODO(Subv): Research and implement these methods.
+        LOG_ERROR(HW_GPU, "Special buffer methods other than Bind are not implemented");
+        return;
+    }
+
+    ASSERT(bound_engines.find(subchannel) != bound_engines.end());
+
+    const EngineID engine = bound_engines[subchannel];
+
+    switch (engine) {
+    case EngineID::FERMI_TWOD_A:
+        fermi_2d->WriteReg(method, value);
+        break;
+    case EngineID::MAXWELL_B:
+        maxwell_3d->WriteReg(method, value);
+        break;
+    case EngineID::MAXWELL_COMPUTE_B:
+        maxwell_compute->WriteReg(method, value);
+        break;
+    default:
+        UNIMPLEMENTED();
+    }
+}
+
+void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
+    // TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an
+    // application VAddr.
+    const VAddr head_address = memory_manager->PhysicalToVirtualAddress(address);
+    VAddr current_addr = head_address;
+    while (current_addr < head_address + size * sizeof(CommandHeader)) {
+        const CommandHeader header = {Memory::Read32(current_addr)};
+        current_addr += sizeof(u32);
+
+        switch (header.mode.Value()) {
+        case SubmissionMode::IncreasingOld:
+        case SubmissionMode::Increasing: {
+            // Increase the method value with each argument.
+            for (unsigned i = 0; i < header.arg_count; ++i) {
+                WriteReg(header.method + i, header.subchannel, Memory::Read32(current_addr));
+                current_addr += sizeof(u32);
+            }
+            break;
+        }
+        case SubmissionMode::NonIncreasingOld:
+        case SubmissionMode::NonIncreasing: {
+            // Use the same method value for all arguments.
+            for (unsigned i = 0; i < header.arg_count; ++i) {
+                WriteReg(header.method, header.subchannel, Memory::Read32(current_addr));
+                current_addr += sizeof(u32);
+            }
+            break;
+        }
+        case SubmissionMode::IncreaseOnce: {
+            ASSERT(header.arg_count.Value() >= 1);
+            // Use the original method for the first argument and then the next method for all other
+            // arguments.
+            WriteReg(header.method, header.subchannel, Memory::Read32(current_addr));
+            current_addr += sizeof(u32);
+            // Use the same method value for all arguments.
+            for (unsigned i = 1; i < header.arg_count; ++i) {
+                WriteReg(header.method + 1, header.subchannel, Memory::Read32(current_addr));
+                current_addr += sizeof(u32);
+            }
+            break;
+        }
+        case SubmissionMode::Inline: {
+            // The register value is stored in the bits 16-28 as an immediate
+            WriteReg(header.method, header.subchannel, header.inline_data);
+            break;
+        }
+        default:
+            UNIMPLEMENTED();
+        }
+    }
+}
+
+} // namespace Tegra

src/video_core/command_processor.h

@@ -0,0 +1,39 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include <type_traits>
+#include "common/bit_field.h"
+#include "common/common_types.h"
+
+namespace Tegra {
+
+enum class SubmissionMode : u32 {
+    IncreasingOld = 0,
+    Increasing = 1,
+    NonIncreasingOld = 2,
+    NonIncreasing = 3,
+    Inline = 4,
+    IncreaseOnce = 5
+};
+
+union CommandHeader {
+    u32 hex;
+
+    BitField<0, 13, u32> method;
+    BitField<13, 3, u32> subchannel;
+
+    BitField<16, 13, u32> arg_count;
+    BitField<16, 13, u32> inline_data;
+
+    BitField<29, 3, SubmissionMode> mode;
+};
+static_assert(std::is_standard_layout<CommandHeader>::value == true,
+              "CommandHeader does not use standard layout");
+static_assert(sizeof(CommandHeader) == sizeof(u32), "CommandHeader has incorrect size!");
+
+void ProcessCommandList(VAddr address, u32 size);
+
+} // namespace Tegra

src/video_core/engines/fermi_2d.cpp

@@ -0,0 +1,13 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "video_core/engines/fermi_2d.h"
+
+namespace Tegra {
+namespace Engines {
+
+void Fermi2D::WriteReg(u32 method, u32 value) {}
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/fermi_2d.h

@@ -0,0 +1,22 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include "common/common_types.h"
+
+namespace Tegra {
+namespace Engines {
+
+class Fermi2D final {
+public:
+    Fermi2D() = default;
+    ~Fermi2D() = default;
+
+    /// Write the value to the register identified by method.
+    void WriteReg(u32 method, u32 value);
+};
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_3d.cpp

@@ -0,0 +1,13 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "video_core/engines/maxwell_3d.h"
+
+namespace Tegra {
+namespace Engines {
+
+void Maxwell3D::WriteReg(u32 method, u32 value) {}
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_3d.h

@@ -0,0 +1,22 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include "common/common_types.h"
+
+namespace Tegra {
+namespace Engines {
+
+class Maxwell3D final {
+public:
+    Maxwell3D() = default;
+    ~Maxwell3D() = default;
+
+    /// Write the value to the register identified by method.
+    void WriteReg(u32 method, u32 value);
+};
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_compute.cpp

@@ -0,0 +1,13 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "video_core/engines/maxwell_compute.h"
+
+namespace Tegra {
+namespace Engines {
+
+void MaxwellCompute::WriteReg(u32 method, u32 value) {}
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/engines/maxwell_compute.h

@@ -0,0 +1,22 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include "common/common_types.h"
+
+namespace Tegra {
+namespace Engines {
+
+class MaxwellCompute final {
+public:
+    MaxwellCompute() = default;
+    ~MaxwellCompute() = default;
+
+    /// Write the value to the register identified by method.
+    void WriteReg(u32 method, u32 value);
+};
+
+} // namespace Engines
+} // namespace Tegra

src/video_core/gpu.h

@@ -0,0 +1,55 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include <memory>
+#include <unordered_map>
+#include "common/common_types.h"
+#include "video_core/engines/fermi_2d.h"
+#include "video_core/engines/maxwell_3d.h"
+#include "video_core/engines/maxwell_compute.h"
+#include "video_core/memory_manager.h"
+
+namespace Tegra {
+
+enum class EngineID {
+    FERMI_TWOD_A = 0x902D, // 2D Engine
+    MAXWELL_B = 0xB197,    // 3D Engine
+    MAXWELL_COMPUTE_B = 0xB1C0,
+    KEPLER_INLINE_TO_MEMORY_B = 0xA140,
+    MAXWELL_DMA_COPY_A = 0xB0B5,
+};
+
+class GPU final {
+public:
+    GPU() {
+        memory_manager = std::make_unique<MemoryManager>();
+        maxwell_3d = std::make_unique<Engines::Maxwell3D>();
+        fermi_2d = std::make_unique<Engines::Fermi2D>();
+        maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
+    }
+    ~GPU() = default;
+
+    /// Processes a command list stored at the specified address in GPU memory.
+    void ProcessCommandList(GPUVAddr address, u32 size);
+
+    std::unique_ptr<MemoryManager> memory_manager;
+
+private:
+    /// Writes a single register in the engine bound to the specified subchannel
+    void WriteReg(u32 method, u32 subchannel, u32 value);
+
+    /// Mapping of command subchannels to their bound engine ids.
+    std::unordered_map<u32, EngineID> bound_engines;
+
+    /// 3D engine
+    std::unique_ptr<Engines::Maxwell3D> maxwell_3d;
+    /// 2D engine
+    std::unique_ptr<Engines::Fermi2D> fermi_2d;
+    /// Compute engine
+    std::unique_ptr<Engines::MaxwellCompute> maxwell_compute;
+};
+
+} // namespace Tegra

src/video_core/memory_manager.cpp

@@ -0,0 +1,110 @@
+// Copyright 2018 yuzu emulator team
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "common/assert.h"
+#include "video_core/memory_manager.h"
+
+namespace Tegra {
+
+PAddr MemoryManager::AllocateSpace(u64 size, u64 align) {
+    boost::optional<PAddr> paddr = FindFreeBlock(size, align);
+    ASSERT(paddr);
+
+    for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) {
+        PageSlot(*paddr + offset) = static_cast<u64>(PageStatus::Allocated);
+    }
+
+    return *paddr;
+}
+
+PAddr MemoryManager::AllocateSpace(PAddr paddr, u64 size, u64 align) {
+    for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) {
+        if (IsPageMapped(paddr + offset)) {
+            return AllocateSpace(size, align);
+        }
+    }
+
+    for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) {
+        PageSlot(paddr + offset) = static_cast<u64>(PageStatus::Allocated);
+    }
+
+    return paddr;
+}
+
+PAddr MemoryManager::MapBufferEx(VAddr vaddr, u64 size) {
+    vaddr &= ~Memory::PAGE_MASK;
+
+    boost::optional<PAddr> paddr = FindFreeBlock(size);
+    ASSERT(paddr);
+
+    for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) {
+        PageSlot(*paddr + offset) = vaddr + offset;
+    }
+
+    return *paddr;
+}
+
+PAddr MemoryManager::MapBufferEx(VAddr vaddr, PAddr paddr, u64 size) {
+    vaddr &= ~Memory::PAGE_MASK;
+    paddr &= ~Memory::PAGE_MASK;
+
+    for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) {
+        if (PageSlot(paddr + offset) != static_cast<u64>(PageStatus::Allocated)) {
+            return MapBufferEx(vaddr, size);
+        }
+    }
+
+    for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) {
+        PageSlot(paddr + offset) = vaddr + offset;
+    }
+
+    return paddr;
+}
+
+boost::optional<PAddr> MemoryManager::FindFreeBlock(u64 size, u64 align) {
+    PAddr paddr{};
+    u64 free_space{};
+    align = (align + Memory::PAGE_MASK) & ~Memory::PAGE_MASK;
+
+    while (paddr + free_space < MAX_ADDRESS) {
+        if (!IsPageMapped(paddr + free_space)) {
+            free_space += Memory::PAGE_SIZE;
+            if (free_space >= size) {
+                return paddr;
+            }
+        } else {
+            paddr += free_space + Memory::PAGE_SIZE;
+            free_space = 0;
+            const u64 remainder{paddr % align};
+            if (!remainder) {
+                paddr = (paddr - remainder) + align;
+            }
+        }
+    }
+
+    return {};
+}
+
+VAddr MemoryManager::PhysicalToVirtualAddress(PAddr paddr) {
+    VAddr base_addr = PageSlot(paddr);
+    ASSERT(base_addr != static_cast<u64>(PageStatus::Unmapped));
+    return base_addr + (paddr & Memory::PAGE_MASK);
+}
+
+bool MemoryManager::IsPageMapped(PAddr paddr) {
+    return PageSlot(paddr) != static_cast<u64>(PageStatus::Unmapped);
+}
+
+VAddr& MemoryManager::PageSlot(PAddr paddr) {
+    auto& block = page_table[(paddr >> (Memory::PAGE_BITS + PAGE_TABLE_BITS)) & PAGE_TABLE_MASK];
+    if (!block) {
+        block = std::make_unique<PageBlock>();
+        for (unsigned index = 0; index < PAGE_BLOCK_SIZE; index++) {
+            (*block)[index] = static_cast<u64>(PageStatus::Unmapped);
+        }
+    }
+    return (*block)[(paddr >> Memory::PAGE_BITS) & PAGE_BLOCK_MASK];
+}
+
+} // namespace Tegra

src/video_core/memory_manager.h

@@ -0,0 +1,49 @@
+// Copyright 2018 yuzu emulator team
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include <array>
+#include <memory>
+#include "common/common_types.h"
+#include "core/memory.h"
+
+namespace Tegra {
+
+/// Virtual addresses in the GPU's memory map are 64 bit.
+using GPUVAddr = u64;
+
+class MemoryManager final {
+public:
+    MemoryManager() = default;
+
+    PAddr AllocateSpace(u64 size, u64 align);
+    PAddr AllocateSpace(PAddr paddr, u64 size, u64 align);
+    PAddr MapBufferEx(VAddr vaddr, u64 size);
+    PAddr MapBufferEx(VAddr vaddr, PAddr paddr, u64 size);
+    VAddr PhysicalToVirtualAddress(PAddr paddr);
+
+private:
+    boost::optional<PAddr> FindFreeBlock(u64 size, u64 align = 1);
+    bool IsPageMapped(PAddr paddr);
+    VAddr& PageSlot(PAddr paddr);
+
+    enum class PageStatus : u64 {
+        Unmapped = 0xFFFFFFFFFFFFFFFFULL,
+        Allocated = 0xFFFFFFFFFFFFFFFEULL,
+    };
+
+    static constexpr u64 MAX_ADDRESS{0x10000000000ULL};
+    static constexpr u64 PAGE_TABLE_BITS{14};
+    static constexpr u64 PAGE_TABLE_SIZE{1 << PAGE_TABLE_BITS};
+    static constexpr u64 PAGE_TABLE_MASK{PAGE_TABLE_SIZE - 1};
+    static constexpr u64 PAGE_BLOCK_BITS{14};
+    static constexpr u64 PAGE_BLOCK_SIZE{1 << PAGE_BLOCK_BITS};
+    static constexpr u64 PAGE_BLOCK_MASK{PAGE_BLOCK_SIZE - 1};
+
+    using PageBlock = std::array<VAddr, PAGE_BLOCK_SIZE>;
+    std::array<std::unique_ptr<PageBlock>, PAGE_TABLE_SIZE> page_table{};
+};
+
+} // namespace Tegra