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shader: Support SSA loops on IR

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This commit is contained in:
ReinUsesLisp
2021-02-14 20:15:42 -03:00
committed by ameerj
parent 8af9297f09
commit cbfb7d182a
12 changed files with 150 additions and 46 deletions
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12
src/shader_recompiler/backend/spirv/emit_spirv.h
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@ -159,10 +159,10 @@ private:
Id EmitWorkgroupId(EmitContext& ctx);
Id EmitLocalInvocationId(EmitContext& ctx);
Id EmitUndefU1(EmitContext& ctx);
void EmitUndefU8(EmitContext& ctx);
void EmitUndefU16(EmitContext& ctx);
void EmitUndefU32(EmitContext& ctx);
void EmitUndefU64(EmitContext& ctx);
Id EmitUndefU8(EmitContext& ctx);
Id EmitUndefU16(EmitContext& ctx);
Id EmitUndefU32(EmitContext& ctx);
Id EmitUndefU64(EmitContext& ctx);
void EmitLoadGlobalU8(EmitContext& ctx);
void EmitLoadGlobalS8(EmitContext& ctx);
void EmitLoadGlobalU16(EmitContext& ctx);
@ -297,12 +297,12 @@ private:
void EmitBitFieldInsert(EmitContext& ctx);
void EmitBitFieldSExtract(EmitContext& ctx);
Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
void EmitSLessThan(EmitContext& ctx);
Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
void EmitULessThan(EmitContext& ctx);
void EmitIEqual(EmitContext& ctx);
void EmitSLessThanEqual(EmitContext& ctx);
void EmitULessThanEqual(EmitContext& ctx);
void EmitSGreaterThan(EmitContext& ctx);
Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs);
void EmitUGreaterThan(EmitContext& ctx);
void EmitINotEqual(EmitContext& ctx);
void EmitSGreaterThanEqual(EmitContext& ctx);

8
src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
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@ -73,8 +73,8 @@ Id EmitSPIRV::EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id coun
return ctx.OpBitFieldUExtract(ctx.u32[1], base, offset, count);
}
void EmitSPIRV::EmitSLessThan(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
Id EmitSPIRV::EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpSLessThan(ctx.u1, lhs, rhs);
}
void EmitSPIRV::EmitULessThan(EmitContext&) {
@ -93,8 +93,8 @@ void EmitSPIRV::EmitULessThanEqual(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
}
void EmitSPIRV::EmitSGreaterThan(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
Id EmitSPIRV::EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpSGreaterThan(ctx.u1, lhs, rhs);
}
void EmitSPIRV::EmitUGreaterThan(EmitContext&) {

10
src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp
View File

@ -10,19 +10,19 @@ Id EmitSPIRV::EmitUndefU1(EmitContext& ctx) {
return ctx.OpUndef(ctx.u1);
}
void EmitSPIRV::EmitUndefU8(EmitContext&) {
Id EmitSPIRV::EmitUndefU8(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
}
void EmitSPIRV::EmitUndefU16(EmitContext&) {
Id EmitSPIRV::EmitUndefU16(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
}
void EmitSPIRV::EmitUndefU32(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
Id EmitSPIRV::EmitUndefU32(EmitContext& ctx) {
return ctx.OpUndef(ctx.u32[1]);
}
void EmitSPIRV::EmitUndefU64(EmitContext&) {
Id EmitSPIRV::EmitUndefU64(EmitContext&) {
throw NotImplementedException("SPIR-V Instruction");
}