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GPU: Cleanup register definitions.
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@ -123,9 +123,9 @@ void TriggerCmdReqQueue(Service::Interface* self) {
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break;
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case GXCommandId::SET_COMMAND_LIST_LAST:
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GPU::Write<u32>(GPU::CommandListAddress, cmd_buff[1] >> 3);
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GPU::Write<u32>(GPU::CommandListSize, cmd_buff[2] >> 3);
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GPU::Write<u32>(GPU::ProcessCommandList, 1); // TODO: Not sure if we are supposed to always write this
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GPU::Write<u32>(GPU::Registers::CommandListAddress, cmd_buff[1] >> 3);
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GPU::Write<u32>(GPU::Registers::CommandListSize, cmd_buff[2] >> 3);
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GPU::Write<u32>(GPU::Registers::ProcessCommandList, 1); // TODO: Not sure if we are supposed to always write this
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break;
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case GXCommandId::SET_MEMORY_FILL:
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