mirror of
https://github.com/yuzu-emu/yuzu-android.git
synced 2025-06-13 16:07:57 -05:00
Sources: Run clang-format on everything.
This commit is contained in:
Emmanuel Gil Peyrot
@ -5,16 +5,16 @@
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#include "common/bit_field.h"
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#include "common/microprofile.h"
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#include "core/memory.h"
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#include "core/hle/kernel/event.h"
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#include "core/hle/kernel/shared_memory.h"
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#include "core/hle/result.h"
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#include "core/hw/hw.h"
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#include "core/hw/gpu.h"
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#include "core/hw/hw.h"
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#include "core/hw/lcd.h"
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#include "core/memory.h"
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#include "video_core/gpu_debugger.h"
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#include "video_core/debug_utils/debug_utils.h"
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#include "video_core/gpu_debugger.h"
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#include "gsp_gpu.h"
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@ -29,12 +29,16 @@ const static u32 REGS_BEGIN = 0x1EB00000;
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namespace GSP_GPU {
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const ResultCode ERR_GSP_REGS_OUTOFRANGE_OR_MISALIGNED(ErrorDescription::OutofRangeOrMisalignedAddress, ErrorModule::GX,
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ErrorSummary::InvalidArgument, ErrorLevel::Usage); // 0xE0E02A01
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const ResultCode
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ERR_GSP_REGS_OUTOFRANGE_OR_MISALIGNED(ErrorDescription::OutofRangeOrMisalignedAddress,
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ErrorModule::GX, ErrorSummary::InvalidArgument,
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ErrorLevel::Usage); // 0xE0E02A01
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const ResultCode ERR_GSP_REGS_MISALIGNED(ErrorDescription::MisalignedSize, ErrorModule::GX,
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ErrorSummary::InvalidArgument, ErrorLevel::Usage); // 0xE0E02BF2
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ErrorSummary::InvalidArgument,
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ErrorLevel::Usage); // 0xE0E02BF2
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const ResultCode ERR_GSP_REGS_INVALID_SIZE(ErrorDescription::InvalidSize, ErrorModule::GX,
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ErrorSummary::InvalidArgument, ErrorLevel::Usage); // 0xE0E02BEC
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ErrorSummary::InvalidArgument,
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ErrorLevel::Usage); // 0xE0E02BEC
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/// Event triggered when GSP interrupt has been signalled
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Kernel::SharedPtr<Kernel::Event> g_interrupt_event;
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@ -73,7 +77,8 @@ static inline InterruptRelayQueue* GetInterruptRelayQueue(u32 thread_id) {
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* @param data Data to be written
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*/
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static void WriteSingleHWReg(u32 base_address, u32 data) {
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DEBUG_ASSERT_MSG((base_address & 3) == 0 && base_address < 0x420000, "Write address out of range or misaligned");
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DEBUG_ASSERT_MSG((base_address & 3) == 0 && base_address < 0x420000,
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"Write address out of range or misaligned");
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HW::Write<u32>(base_address + REGS_BEGIN, data);
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}
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@ -90,7 +95,8 @@ static ResultCode WriteHWRegs(u32 base_address, u32 size_in_bytes, VAddr data_va
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const u32 max_size_in_bytes = 0x80;
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if (base_address & 3 || base_address >= 0x420000) {
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LOG_ERROR(Service_GSP, "Write address was out of range or misaligned! (address=0x%08x, size=0x%08x)",
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LOG_ERROR(Service_GSP,
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"Write address was out of range or misaligned! (address=0x%08x, size=0x%08x)",
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base_address, size_in_bytes);
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return ERR_GSP_REGS_OUTOFRANGE_OR_MISALIGNED;
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} else if (size_in_bytes <= max_size_in_bytes) {
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@ -124,12 +130,14 @@ static ResultCode WriteHWRegs(u32 base_address, u32 size_in_bytes, VAddr data_va
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* @param masks A pointer to the masks
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* @return RESULT_SUCCESS if the parameters are valid, error code otherwise
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*/
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static ResultCode WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, VAddr data_vaddr, VAddr masks_vaddr) {
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static ResultCode WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, VAddr data_vaddr,
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VAddr masks_vaddr) {
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// This magic number is verified to be done by the gsp module
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const u32 max_size_in_bytes = 0x80;
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if (base_address & 3 || base_address >= 0x420000) {
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LOG_ERROR(Service_GSP, "Write address was out of range or misaligned! (address=0x%08x, size=0x%08x)",
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LOG_ERROR(Service_GSP,
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"Write address was out of range or misaligned! (address=0x%08x, size=0x%08x)",
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base_address, size_in_bytes);
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return ERR_GSP_REGS_OUTOFRANGE_OR_MISALIGNED;
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} else if (size_in_bytes <= max_size_in_bytes) {
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@ -214,7 +222,8 @@ static void ReadHWRegs(Service::Interface* self) {
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// TODO: Return proper error codes
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if (reg_addr + size >= 0x420000) {
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LOG_ERROR(Service_GSP, "Read address out of range! (address=0x%08x, size=0x%08x)", reg_addr, size);
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LOG_ERROR(Service_GSP, "Read address out of range! (address=0x%08x, size=0x%08x)", reg_addr,
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size);
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return;
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}
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@ -243,22 +252,34 @@ ResultCode SetBufferSwap(u32 screen_id, const FrameBufferInfo& info) {
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PAddr phys_address_left = Memory::VirtualToPhysicalAddress(info.address_left);
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PAddr phys_address_right = Memory::VirtualToPhysicalAddress(info.address_right);
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if (info.active_fb == 0) {
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WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left1)),
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phys_address_left);
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WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right1)),
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phys_address_right);
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WriteSingleHWReg(
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base_address +
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4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left1)),
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phys_address_left);
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WriteSingleHWReg(
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base_address +
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4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right1)),
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phys_address_right);
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} else {
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WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left2)),
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phys_address_left);
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WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right2)),
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phys_address_right);
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WriteSingleHWReg(
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base_address +
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4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left2)),
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phys_address_left);
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WriteSingleHWReg(
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base_address +
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4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right2)),
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phys_address_right);
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}
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WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].stride)),
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WriteSingleHWReg(base_address +
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4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].stride)),
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info.stride);
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WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].color_format)),
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info.format);
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WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].active_fb)),
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info.shown_fb);
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WriteSingleHWReg(
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base_address +
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4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].color_format)),
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info.format);
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WriteSingleHWReg(
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base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].active_fb)),
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info.shown_fb);
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if (Pica::g_debug_context)
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Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::BufferSwapped, nullptr);
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@ -305,15 +326,15 @@ static void SetBufferSwap(Service::Interface* self) {
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static void FlushDataCache(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32 address = cmd_buff[1];
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u32 size = cmd_buff[2];
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u32 size = cmd_buff[2];
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u32 process = cmd_buff[4];
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// TODO(purpasmart96): Verify return header on HW
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cmd_buff[1] = RESULT_SUCCESS.raw; // No error
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LOG_DEBUG(Service_GSP, "(STUBBED) called address=0x%08X, size=0x%08X, process=0x%08X",
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address, size, process);
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LOG_DEBUG(Service_GSP, "(STUBBED) called address=0x%08X, size=0x%08X, process=0x%08X", address,
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size, process);
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}
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/**
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@ -356,11 +377,12 @@ static void RegisterInterruptRelayQueue(Service::Interface* self) {
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// This specific code is required for a successful initialization, rather than 0
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first_initialization = false;
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cmd_buff[1] = ResultCode(ErrorDescription::GPU_FirstInitialization, ErrorModule::GX,
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ErrorSummary::Success, ErrorLevel::Success).raw;
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ErrorSummary::Success, ErrorLevel::Success)
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.raw;
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} else {
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cmd_buff[1] = RESULT_SUCCESS.raw;
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}
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cmd_buff[2] = g_thread_id++; // Thread ID
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cmd_buff[2] = g_thread_id++; // Thread ID
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cmd_buff[4] = Kernel::g_handle_table.Create(g_shared_memory).MoveFrom(); // GSP shared memory
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g_interrupt_event->Signal(); // TODO(bunnei): Is this correct?
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@ -416,7 +438,8 @@ void SignalInterrupt(InterruptId interrupt_id) {
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// Update framebuffer information if requested
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// TODO(yuriks): Confirm where this code should be called. It is definitely updated without
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// executing any GSP commands, only waiting on the event.
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int screen_id = (interrupt_id == InterruptId::PDC0) ? 0 : (interrupt_id == InterruptId::PDC1) ? 1 : -1;
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int screen_id =
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(interrupt_id == InterruptId::PDC0) ? 0 : (interrupt_id == InterruptId::PDC1) ? 1 : -1;
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if (screen_id != -1) {
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FrameBufferUpdate* info = GetFrameBufferInfo(thread_id, screen_id);
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if (info->is_dirty) {
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@ -440,25 +463,27 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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switch (command.id) {
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// GX request DMA - typically used for copying memory from GSP heap to VRAM
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case CommandId::REQUEST_DMA:
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{
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case CommandId::REQUEST_DMA: {
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MICROPROFILE_SCOPE(GPU_GSP_DMA);
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// TODO: Consider attempting rasterizer-accelerated surface blit if that usage is ever possible/likely
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Memory::RasterizerFlushRegion(Memory::VirtualToPhysicalAddress(command.dma_request.source_address),
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command.dma_request.size);
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Memory::RasterizerFlushAndInvalidateRegion(Memory::VirtualToPhysicalAddress(command.dma_request.dest_address),
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command.dma_request.size);
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// TODO: Consider attempting rasterizer-accelerated surface blit if that usage is ever
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// possible/likely
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Memory::RasterizerFlushRegion(
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Memory::VirtualToPhysicalAddress(command.dma_request.source_address),
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command.dma_request.size);
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Memory::RasterizerFlushAndInvalidateRegion(
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Memory::VirtualToPhysicalAddress(command.dma_request.dest_address),
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command.dma_request.size);
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// TODO(Subv): These memory accesses should not go through the application's memory mapping.
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// They should go through the GSP module's memory mapping.
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Memory::CopyBlock(command.dma_request.dest_address, command.dma_request.source_address, command.dma_request.size);
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Memory::CopyBlock(command.dma_request.dest_address, command.dma_request.source_address,
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command.dma_request.size);
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SignalInterrupt(InterruptId::DMA);
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break;
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}
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// TODO: This will need some rework in the future. (why?)
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case CommandId::SUBMIT_GPU_CMDLIST:
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{
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case CommandId::SUBMIT_GPU_CMDLIST: {
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auto& params = command.submit_gpu_cmdlist;
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if (params.do_flush) {
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@ -468,10 +493,12 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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}
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(command_processor_config.address)),
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Memory::VirtualToPhysicalAddress(params.address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(command_processor_config.size)), params.size);
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Memory::VirtualToPhysicalAddress(params.address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(command_processor_config.size)),
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params.size);
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// TODO: Not sure if we are supposed to always write this .. seems to trigger processing though
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// TODO: Not sure if we are supposed to always write this .. seems to trigger processing
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// though
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(command_processor_config.trigger)), 1);
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// TODO(yuriks): Figure out the meaning of the `flags` field.
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@ -481,67 +508,70 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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// It's assumed that the two "blocks" behave equivalently.
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// Presumably this is done simply to allow two memory fills to run in parallel.
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case CommandId::SET_MEMORY_FILL:
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{
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case CommandId::SET_MEMORY_FILL: {
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auto& params = command.memory_fill;
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if (params.start1 != 0) {
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_start)),
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Memory::VirtualToPhysicalAddress(params.start1) >> 3);
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Memory::VirtualToPhysicalAddress(params.start1) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_end)),
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Memory::VirtualToPhysicalAddress(params.end1) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].value_32bit)), params.value1);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].control)), params.control1);
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Memory::VirtualToPhysicalAddress(params.end1) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].value_32bit)),
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params.value1);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].control)),
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params.control1);
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}
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if (params.start2 != 0) {
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_start)),
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Memory::VirtualToPhysicalAddress(params.start2) >> 3);
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Memory::VirtualToPhysicalAddress(params.start2) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_end)),
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Memory::VirtualToPhysicalAddress(params.end2) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].value_32bit)), params.value2);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].control)), params.control2);
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Memory::VirtualToPhysicalAddress(params.end2) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].value_32bit)),
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params.value2);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].control)),
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params.control2);
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}
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break;
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}
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case CommandId::SET_DISPLAY_TRANSFER:
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{
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case CommandId::SET_DISPLAY_TRANSFER: {
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auto& params = command.display_transfer;
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
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Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
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Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
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Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)), params.in_buffer_size);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)), params.out_buffer_size);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.flags)), params.flags);
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Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)),
|
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params.in_buffer_size);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)),
|
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params.out_buffer_size);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.flags)),
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params.flags);
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WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.trigger)), 1);
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break;
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}
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case CommandId::SET_TEXTURE_COPY:
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{
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case CommandId::SET_TEXTURE_COPY: {
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auto& params = command.texture_copy;
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.input_address),
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Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
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Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.output_address),
|
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Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
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Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
|
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.texture_copy.size),
|
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params.size);
|
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params.size);
|
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.texture_copy.input_size),
|
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params.in_width_gap);
|
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params.in_width_gap);
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.texture_copy.output_size),
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params.out_width_gap);
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.flags),
|
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params.flags);
|
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params.out_width_gap);
|
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.flags), params.flags);
|
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|
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// NOTE: Actual GSP ORs 1 with current register instead of overwriting. Doesn't seem to matter.
|
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// NOTE: Actual GSP ORs 1 with current register instead of overwriting. Doesn't seem to
|
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// matter.
|
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WriteGPURegister((u32)GPU_REG_INDEX(display_transfer_config.trigger), 1);
|
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break;
|
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}
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case CommandId::CACHE_FLUSH:
|
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{
|
||||
case CommandId::CACHE_FLUSH: {
|
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// NOTE: Rasterizer flushing handled elsewhere in CPU read/write and other GPU handlers
|
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// Use command.cache_flush.regions to implement this handler
|
||||
break;
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@ -552,7 +582,8 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
|
||||
}
|
||||
|
||||
if (Pica::g_debug_context)
|
||||
Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::GSPCommandProcessed, (void*)&command);
|
||||
Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::GSPCommandProcessed,
|
||||
(void*)&command);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -575,7 +606,7 @@ static void SetLcdForceBlack(Service::Interface* self) {
|
||||
// the color to black (all zero).
|
||||
data.is_enabled.Assign(enable_black);
|
||||
|
||||
LCD::Write(HW::VADDR_LCD + 4 * LCD_REG_INDEX(color_fill_top), data.raw); // Top LCD
|
||||
LCD::Write(HW::VADDR_LCD + 4 * LCD_REG_INDEX(color_fill_top), data.raw); // Top LCD
|
||||
LCD::Write(HW::VADDR_LCD + 4 * LCD_REG_INDEX(color_fill_bottom), data.raw); // Bottom LCD
|
||||
|
||||
cmd_buff[1] = RESULT_SUCCESS.raw;
|
||||
@ -679,37 +710,37 @@ static void ReleaseRight(Service::Interface* self) {
|
||||
}
|
||||
|
||||
const Interface::FunctionInfo FunctionTable[] = {
|
||||
{0x00010082, WriteHWRegs, "WriteHWRegs"},
|
||||
{0x00020084, WriteHWRegsWithMask, "WriteHWRegsWithMask"},
|
||||
{0x00030082, nullptr, "WriteHWRegRepeat"},
|
||||
{0x00040080, ReadHWRegs, "ReadHWRegs"},
|
||||
{0x00050200, SetBufferSwap, "SetBufferSwap"},
|
||||
{0x00060082, nullptr, "SetCommandList"},
|
||||
{0x000700C2, nullptr, "RequestDma"},
|
||||
{0x00080082, FlushDataCache, "FlushDataCache"},
|
||||
{0x00090082, nullptr, "InvalidateDataCache"},
|
||||
{0x000A0044, nullptr, "RegisterInterruptEvents"},
|
||||
{0x000B0040, SetLcdForceBlack, "SetLcdForceBlack"},
|
||||
{0x000C0000, TriggerCmdReqQueue, "TriggerCmdReqQueue"},
|
||||
{0x000D0140, nullptr, "SetDisplayTransfer"},
|
||||
{0x000E0180, nullptr, "SetTextureCopy"},
|
||||
{0x000F0200, nullptr, "SetMemoryFill"},
|
||||
{0x00100040, SetAxiConfigQoSMode, "SetAxiConfigQoSMode"},
|
||||
{0x00110040, nullptr, "SetPerfLogMode"},
|
||||
{0x00120000, nullptr, "GetPerfLog"},
|
||||
{0x00130042, RegisterInterruptRelayQueue, "RegisterInterruptRelayQueue"},
|
||||
{0x00010082, WriteHWRegs, "WriteHWRegs"},
|
||||
{0x00020084, WriteHWRegsWithMask, "WriteHWRegsWithMask"},
|
||||
{0x00030082, nullptr, "WriteHWRegRepeat"},
|
||||
{0x00040080, ReadHWRegs, "ReadHWRegs"},
|
||||
{0x00050200, SetBufferSwap, "SetBufferSwap"},
|
||||
{0x00060082, nullptr, "SetCommandList"},
|
||||
{0x000700C2, nullptr, "RequestDma"},
|
||||
{0x00080082, FlushDataCache, "FlushDataCache"},
|
||||
{0x00090082, nullptr, "InvalidateDataCache"},
|
||||
{0x000A0044, nullptr, "RegisterInterruptEvents"},
|
||||
{0x000B0040, SetLcdForceBlack, "SetLcdForceBlack"},
|
||||
{0x000C0000, TriggerCmdReqQueue, "TriggerCmdReqQueue"},
|
||||
{0x000D0140, nullptr, "SetDisplayTransfer"},
|
||||
{0x000E0180, nullptr, "SetTextureCopy"},
|
||||
{0x000F0200, nullptr, "SetMemoryFill"},
|
||||
{0x00100040, SetAxiConfigQoSMode, "SetAxiConfigQoSMode"},
|
||||
{0x00110040, nullptr, "SetPerfLogMode"},
|
||||
{0x00120000, nullptr, "GetPerfLog"},
|
||||
{0x00130042, RegisterInterruptRelayQueue, "RegisterInterruptRelayQueue"},
|
||||
{0x00140000, UnregisterInterruptRelayQueue, "UnregisterInterruptRelayQueue"},
|
||||
{0x00150002, nullptr, "TryAcquireRight"},
|
||||
{0x00160042, AcquireRight, "AcquireRight"},
|
||||
{0x00170000, ReleaseRight, "ReleaseRight"},
|
||||
{0x00180000, ImportDisplayCaptureInfo, "ImportDisplayCaptureInfo"},
|
||||
{0x00190000, nullptr, "SaveVramSysArea"},
|
||||
{0x001A0000, nullptr, "RestoreVramSysArea"},
|
||||
{0x001B0000, nullptr, "ResetGpuCore"},
|
||||
{0x001C0040, nullptr, "SetLedForceOff"},
|
||||
{0x001D0040, nullptr, "SetTestCommand"},
|
||||
{0x001E0080, nullptr, "SetInternalPriorities"},
|
||||
{0x001F0082, nullptr, "StoreDataCache"},
|
||||
{0x00150002, nullptr, "TryAcquireRight"},
|
||||
{0x00160042, AcquireRight, "AcquireRight"},
|
||||
{0x00170000, ReleaseRight, "ReleaseRight"},
|
||||
{0x00180000, ImportDisplayCaptureInfo, "ImportDisplayCaptureInfo"},
|
||||
{0x00190000, nullptr, "SaveVramSysArea"},
|
||||
{0x001A0000, nullptr, "RestoreVramSysArea"},
|
||||
{0x001B0000, nullptr, "ResetGpuCore"},
|
||||
{0x001C0040, nullptr, "SetLedForceOff"},
|
||||
{0x001D0040, nullptr, "SetTestCommand"},
|
||||
{0x001E0080, nullptr, "SetInternalPriorities"},
|
||||
{0x001F0082, nullptr, "StoreDataCache"},
|
||||
};
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
@ -721,9 +752,9 @@ Interface::Interface() {
|
||||
g_interrupt_event = nullptr;
|
||||
|
||||
using Kernel::MemoryPermission;
|
||||
g_shared_memory = Kernel::SharedMemory::Create(nullptr, 0x1000,
|
||||
MemoryPermission::ReadWrite, MemoryPermission::ReadWrite,
|
||||
0, Kernel::MemoryRegion::BASE, "GSP:SharedMemory");
|
||||
g_shared_memory = Kernel::SharedMemory::Create(nullptr, 0x1000, MemoryPermission::ReadWrite,
|
||||
MemoryPermission::ReadWrite, 0,
|
||||
Kernel::MemoryRegion::BASE, "GSP:SharedMemory");
|
||||
|
||||
g_thread_id = 0;
|
||||
gpu_right_acquired = false;
|
||||
|
||||
Reference in New Issue
Block a user