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Shader_IR: Implement FLO instruction.
This commit is contained in:
committed by
FernandoS27
parent
95137a04e1
commit
f3d1b370aa
@ -130,6 +130,24 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) {
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::FLO_R:
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case OpCode::Id::FLO_C:
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case OpCode::Id::FLO_IMM: {
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Node value;
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if (instr.flo.invert) {
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op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b);
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}
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if (instr.flo.is_signed) {
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value = Operation(OperationCode::IBitMSB, NO_PRECISE, op_b);
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} else {
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value = Operation(OperationCode::UBitMSB, NO_PRECISE, op_b);
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}
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if (instr.flo.sh) {
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value = Operation(OperationCode::UBitwiseXor, NO_PRECISE, value, Immediate(31));
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}
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::SEL_C:
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case OpCode::Id::SEL_R:
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case OpCode::Id::SEL_IMM: {
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@ -68,6 +68,7 @@ enum class OperationCode {
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IBitfieldInsert, /// (MetaArithmetic, int base, int insert, int offset, int bits) -> int
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IBitfieldExtract, /// (MetaArithmetic, int value, int offset, int offset) -> int
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IBitCount, /// (MetaArithmetic, int) -> int
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IBitMSB, /// (MetaArithmetic, int) -> int
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UAdd, /// (MetaArithmetic, uint a, uint b) -> uint
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UMul, /// (MetaArithmetic, uint a, uint b) -> uint
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@ -86,6 +87,7 @@ enum class OperationCode {
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UBitfieldInsert, /// (MetaArithmetic, uint base, uint insert, int offset, int bits) -> uint
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UBitfieldExtract, /// (MetaArithmetic, uint value, int offset, int offset) -> uint
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UBitCount, /// (MetaArithmetic, uint) -> uint
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UBitMSB, /// (MetaArithmetic, uint) -> uint
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HAdd, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HMul, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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