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Merge pull request #193 from N00byKing/3184_2_robotic_boogaloo
Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
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@ -122,11 +122,22 @@ std::unique_ptr<Dynarmic::A64::Jit> MakeJit(const std::unique_ptr<ARM_Dynarmic_C
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return std::make_unique<Dynarmic::A64::Jit>(config);
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}
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void ARM_Dynarmic::Run() {
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ASSERT(Memory::GetCurrentPageTable() == current_page_table);
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jit->Run();
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}
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void ARM_Dynarmic::Step() {
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cb->InterpreterFallback(jit->GetPC(), 1);
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}
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ARM_Dynarmic::ARM_Dynarmic()
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: cb(std::make_unique<ARM_Dynarmic_Callbacks>(*this)), jit(MakeJit(cb)) {
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ARM_Interface::ThreadContext ctx;
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inner_unicorn.SaveContext(ctx);
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LoadContext(ctx);
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PageTableChanged();
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}
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ARM_Dynarmic::~ARM_Dynarmic() = default;
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@ -189,13 +200,6 @@ void ARM_Dynarmic::SetTlsAddress(u64 address) {
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cb->tpidrro_el0 = address;
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}
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void ARM_Dynarmic::ExecuteInstructions(int num_instructions) {
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cb->ticks_remaining = num_instructions;
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jit->Run();
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CoreTiming::AddTicks(num_instructions - cb->num_interpreted_instructions);
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cb->num_interpreted_instructions = 0;
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}
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void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
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ctx.cpu_registers = jit->GetRegisters();
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ctx.sp = jit->GetSP();
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@ -228,4 +232,5 @@ void ARM_Dynarmic::ClearInstructionCache() {
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void ARM_Dynarmic::PageTableChanged() {
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jit = MakeJit(cb);
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current_page_table = Memory::GetCurrentPageTable();
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}
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