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GPU: Store shader constbuffer bindings in the GPU state.
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@ -39,6 +39,8 @@ public:
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static constexpr size_t NumVertexArrays = 32;
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static constexpr size_t MaxShaderProgram = 6;
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static constexpr size_t MaxShaderType = 5;
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// Maximum number of const buffers per shader stage.
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static constexpr size_t MaxConstBuffers = 16;
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enum class QueryMode : u32 {
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Write = 0,
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@ -146,12 +148,18 @@ public:
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u32 cb_address_low;
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u32 cb_pos;
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u32 cb_data[NumCBData];
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GPUVAddr BufferAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(cb_address_high) << 32) | cb_address_low);
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}
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} const_buffer;
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INSERT_PADDING_WORDS(0x10);
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struct {
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union {
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u32 raw_config;
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BitField<0, 1, u32> valid;
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BitField<4, 5, u32> index;
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};
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@ -167,14 +175,25 @@ public:
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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struct State {
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struct ShaderInfo {
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struct ConstBufferInfo {
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GPUVAddr address;
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u32 index;
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u32 size;
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bool enabled;
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};
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struct ShaderProgramInfo {
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Regs::ShaderType type;
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Regs::ShaderProgram program;
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GPUVAddr address;
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GPUVAddr cb_address;
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};
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std::array<ShaderInfo, Regs::MaxShaderProgram> shaders;
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struct ShaderStageInfo {
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std::array<ConstBufferInfo, Regs::MaxConstBuffers> const_buffers;
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};
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std::array<ShaderStageInfo, Regs::MaxShaderType> shader_stages;
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std::array<ShaderProgramInfo, Regs::MaxShaderProgram> shader_programs;
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};
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State state{};
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@ -185,6 +204,9 @@ private:
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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/// Handles a write to the CB_BIND register.
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void ProcessCBBind(Regs::ShaderType stage);
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/// Handles a write to the VERTEX_END_GL register, triggering a draw.
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void DrawArrays();
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