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core: Implement separate A32/A64 ARM interfaces.
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bunnei
@ -1,320 +0,0 @@
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// Copyright 2018 yuzu emulator team
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cinttypes>
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#include <memory>
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#include <dynarmic/A64/a64.h>
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#include <dynarmic/A64/config.h>
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#include "common/logging/log.h"
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#include "common/microprofile.h"
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#include "core/arm/dynarmic/arm_dynarmic.h"
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#include "core/core.h"
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#include "core/core_manager.h"
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#include "core/core_timing.h"
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#include "core/core_timing_util.h"
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#include "core/gdbstub/gdbstub.h"
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#include "core/hardware_properties.h"
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#include "core/hle/kernel/process.h"
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#include "core/hle/kernel/scheduler.h"
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#include "core/hle/kernel/svc.h"
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#include "core/hle/kernel/vm_manager.h"
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#include "core/memory.h"
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namespace Core {
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using Vector = Dynarmic::A64::Vector;
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class ARM_Dynarmic_Callbacks : public Dynarmic::A64::UserCallbacks {
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public:
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explicit ARM_Dynarmic_Callbacks(ARM_Dynarmic& parent) : parent(parent) {}
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u8 MemoryRead8(u64 vaddr) override {
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return parent.system.Memory().Read8(vaddr);
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}
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u16 MemoryRead16(u64 vaddr) override {
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return parent.system.Memory().Read16(vaddr);
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}
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u32 MemoryRead32(u64 vaddr) override {
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return parent.system.Memory().Read32(vaddr);
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}
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u64 MemoryRead64(u64 vaddr) override {
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return parent.system.Memory().Read64(vaddr);
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}
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Vector MemoryRead128(u64 vaddr) override {
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auto& memory = parent.system.Memory();
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return {memory.Read64(vaddr), memory.Read64(vaddr + 8)};
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}
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void MemoryWrite8(u64 vaddr, u8 value) override {
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parent.system.Memory().Write8(vaddr, value);
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}
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void MemoryWrite16(u64 vaddr, u16 value) override {
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parent.system.Memory().Write16(vaddr, value);
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}
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void MemoryWrite32(u64 vaddr, u32 value) override {
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parent.system.Memory().Write32(vaddr, value);
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}
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void MemoryWrite64(u64 vaddr, u64 value) override {
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parent.system.Memory().Write64(vaddr, value);
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}
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void MemoryWrite128(u64 vaddr, Vector value) override {
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auto& memory = parent.system.Memory();
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memory.Write64(vaddr, value[0]);
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memory.Write64(vaddr + 8, value[1]);
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}
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void InterpreterFallback(u64 pc, std::size_t num_instructions) override {
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LOG_INFO(Core_ARM, "Unicorn fallback @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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num_instructions, MemoryReadCode(pc));
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ARM_Interface::ThreadContext ctx;
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parent.SaveContext(ctx);
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parent.inner_unicorn.LoadContext(ctx);
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parent.inner_unicorn.ExecuteInstructions(num_instructions);
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parent.inner_unicorn.SaveContext(ctx);
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parent.LoadContext(ctx);
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num_interpreted_instructions += num_instructions;
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}
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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switch (exception) {
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case Dynarmic::A64::Exception::WaitForInterrupt:
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case Dynarmic::A64::Exception::WaitForEvent:
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case Dynarmic::A64::Exception::SendEvent:
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case Dynarmic::A64::Exception::SendEventLocal:
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case Dynarmic::A64::Exception::Yield:
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return;
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case Dynarmic::A64::Exception::Breakpoint:
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if (GDBStub::IsServerEnabled()) {
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parent.jit->HaltExecution();
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parent.SetPC(pc);
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Kernel::Thread* const thread = parent.system.CurrentScheduler().GetCurrentThread();
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parent.SaveContext(thread->GetContext());
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GDBStub::Break();
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GDBStub::SendTrap(thread, 5);
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return;
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}
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[[fallthrough]];
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default:
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ASSERT_MSG(false, "ExceptionRaised(exception = {}, pc = {:X})",
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static_cast<std::size_t>(exception), pc);
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}
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}
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void CallSVC(u32 swi) override {
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Kernel::CallSVC(parent.system, swi);
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}
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void AddTicks(u64 ticks) override {
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// Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a
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// rough approximation of the amount of executed ticks in the system, it may be thrown off
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// if not all cores are doing a similar amount of work. Instead of doing this, we should
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// device a way so that timing is consistent across all cores without increasing the ticks 4
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// times.
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u64 amortized_ticks = (ticks - num_interpreted_instructions) / Core::NUM_CPU_CORES;
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// Always execute at least one tick.
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amortized_ticks = std::max<u64>(amortized_ticks, 1);
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parent.system.CoreTiming().AddTicks(amortized_ticks);
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num_interpreted_instructions = 0;
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}
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u64 GetTicksRemaining() override {
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return std::max(parent.system.CoreTiming().GetDowncount(), s64{0});
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}
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u64 GetCNTPCT() override {
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return Timing::CpuCyclesToClockCycles(parent.system.CoreTiming().GetTicks());
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}
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ARM_Dynarmic& parent;
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std::size_t num_interpreted_instructions = 0;
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u64 tpidrro_el0 = 0;
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u64 tpidr_el0 = 0;
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};
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std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic::MakeJit(Common::PageTable& page_table,
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std::size_t address_space_bits) const {
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Dynarmic::A64::UserConfig config;
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// Callbacks
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config.callbacks = cb.get();
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// Memory
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config.page_table = reinterpret_cast<void**>(page_table.pointers.data());
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config.page_table_address_space_bits = address_space_bits;
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config.silently_mirror_page_table = false;
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config.absolute_offset_page_table = true;
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// Multi-process state
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config.processor_id = core_index;
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config.global_monitor = &exclusive_monitor.monitor;
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// System registers
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config.tpidrro_el0 = &cb->tpidrro_el0;
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config.tpidr_el0 = &cb->tpidr_el0;
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config.dczid_el0 = 4;
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config.ctr_el0 = 0x8444c004;
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config.cntfrq_el0 = Hardware::CNTFREQ;
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// Unpredictable instructions
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config.define_unpredictable_behaviour = true;
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return std::make_shared<Dynarmic::A64::Jit>(config);
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}
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MICROPROFILE_DEFINE(ARM_Jit_Dynarmic, "ARM JIT", "Dynarmic", MP_RGB(255, 64, 64));
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void ARM_Dynarmic::Run() {
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MICROPROFILE_SCOPE(ARM_Jit_Dynarmic);
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jit->Run();
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}
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void ARM_Dynarmic::Step() {
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cb->InterpreterFallback(jit->GetPC(), 1);
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}
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ARM_Dynarmic::ARM_Dynarmic(System& system, ExclusiveMonitor& exclusive_monitor,
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std::size_t core_index)
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: ARM_Interface{system},
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cb(std::make_unique<ARM_Dynarmic_Callbacks>(*this)), inner_unicorn{system},
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core_index{core_index}, exclusive_monitor{
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dynamic_cast<DynarmicExclusiveMonitor&>(exclusive_monitor)} {}
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ARM_Dynarmic::~ARM_Dynarmic() = default;
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void ARM_Dynarmic::SetPC(u64 pc) {
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jit->SetPC(pc);
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}
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u64 ARM_Dynarmic::GetPC() const {
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return jit->GetPC();
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}
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u64 ARM_Dynarmic::GetReg(int index) const {
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return jit->GetRegister(index);
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}
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void ARM_Dynarmic::SetReg(int index, u64 value) {
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jit->SetRegister(index, value);
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}
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u128 ARM_Dynarmic::GetVectorReg(int index) const {
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return jit->GetVector(index);
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}
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void ARM_Dynarmic::SetVectorReg(int index, u128 value) {
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jit->SetVector(index, value);
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}
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u32 ARM_Dynarmic::GetPSTATE() const {
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return jit->GetPstate();
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}
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void ARM_Dynarmic::SetPSTATE(u32 pstate) {
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jit->SetPstate(pstate);
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}
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u64 ARM_Dynarmic::GetTlsAddress() const {
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return cb->tpidrro_el0;
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}
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void ARM_Dynarmic::SetTlsAddress(VAddr address) {
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cb->tpidrro_el0 = address;
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}
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u64 ARM_Dynarmic::GetTPIDR_EL0() const {
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return cb->tpidr_el0;
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}
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void ARM_Dynarmic::SetTPIDR_EL0(u64 value) {
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cb->tpidr_el0 = value;
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}
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void ARM_Dynarmic::SaveContext(ThreadContext& ctx) {
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ctx.cpu_registers = jit->GetRegisters();
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ctx.sp = jit->GetSP();
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ctx.pc = jit->GetPC();
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ctx.pstate = jit->GetPstate();
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ctx.vector_registers = jit->GetVectors();
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ctx.fpcr = jit->GetFpcr();
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ctx.fpsr = jit->GetFpsr();
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ctx.tpidr = cb->tpidr_el0;
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}
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void ARM_Dynarmic::LoadContext(const ThreadContext& ctx) {
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jit->SetRegisters(ctx.cpu_registers);
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jit->SetSP(ctx.sp);
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jit->SetPC(ctx.pc);
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jit->SetPstate(ctx.pstate);
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jit->SetVectors(ctx.vector_registers);
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jit->SetFpcr(ctx.fpcr);
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jit->SetFpsr(ctx.fpsr);
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SetTPIDR_EL0(ctx.tpidr);
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}
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void ARM_Dynarmic::PrepareReschedule() {
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jit->HaltExecution();
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}
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void ARM_Dynarmic::ClearInstructionCache() {
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jit->ClearCache();
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}
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void ARM_Dynarmic::ClearExclusiveState() {
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jit->ClearExclusiveState();
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}
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void ARM_Dynarmic::PageTableChanged(Common::PageTable& page_table,
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std::size_t new_address_space_size_in_bits) {
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auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
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auto iter = jit_cache.find(key);
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if (iter != jit_cache.end()) {
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jit = iter->second;
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return;
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}
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jit = MakeJit(page_table, new_address_space_size_in_bits);
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jit_cache.emplace(key, jit);
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}
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DynarmicExclusiveMonitor::DynarmicExclusiveMonitor(Memory::Memory& memory_, std::size_t core_count)
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: monitor(core_count), memory{memory_} {}
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DynarmicExclusiveMonitor::~DynarmicExclusiveMonitor() = default;
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void DynarmicExclusiveMonitor::SetExclusive(std::size_t core_index, VAddr addr) {
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// Size doesn't actually matter.
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monitor.Mark(core_index, addr, 16);
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}
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void DynarmicExclusiveMonitor::ClearExclusive() {
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monitor.Clear();
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite8(std::size_t core_index, VAddr vaddr, u8 value) {
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return monitor.DoExclusiveOperation(core_index, vaddr, 1, [&] { memory.Write8(vaddr, value); });
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite16(std::size_t core_index, VAddr vaddr, u16 value) {
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return monitor.DoExclusiveOperation(core_index, vaddr, 2,
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[&] { memory.Write16(vaddr, value); });
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite32(std::size_t core_index, VAddr vaddr, u32 value) {
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return monitor.DoExclusiveOperation(core_index, vaddr, 4,
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[&] { memory.Write32(vaddr, value); });
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite64(std::size_t core_index, VAddr vaddr, u64 value) {
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return monitor.DoExclusiveOperation(core_index, vaddr, 8,
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[&] { memory.Write64(vaddr, value); });
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite128(std::size_t core_index, VAddr vaddr, u128 value) {
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return monitor.DoExclusiveOperation(core_index, vaddr, 16, [&] {
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memory.Write64(vaddr + 0, value[0]);
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memory.Write64(vaddr + 8, value[1]);
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});
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}
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} // namespace Core
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