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GPU: Reduce the number of registers of Maxwell3D to 0xE00.

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The rest are just macro shim registers.
This commit is contained in:
Subv
2018-04-23 20:03:50 -05:00
parent a994446b6e
commit c16cfbbc6c
2 changed files with 5 additions and 5 deletions
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4
src/video_core/engines/maxwell_3d.h
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@ -31,7 +31,7 @@ public:
/// Register structure of the Maxwell3D engine.
/// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
struct Regs {
static constexpr size_t NUM_REGS = 0xE36;
static constexpr size_t NUM_REGS = 0xE00;
static constexpr size_t NumRenderTargets = 8;
static constexpr size_t NumViewports = 16;
@ -613,7 +613,7 @@ public:
u32 size[MaxShaderStage];
} tex_info_buffers;
INSERT_PADDING_WORDS(0x102);
INSERT_PADDING_WORDS(0xCC);
};
std::array<u32, NUM_REGS> reg_array;
};