af89723fa3
Shader_Ir: Correct TLD4S encoding and implement f16 flag.
2019-12-11 19:53:17 -04:00
271a3264f3
Shader_Ir: default failed tracks on bindless samplers to null values.
2019-12-11 19:53:16 -04:00
425a254fa2
shader: Implement MEMBAR.GL
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Implement using memoryBarrier in GLSL and OpMemoryBarrier on SPIR-V.
2019-12-10 16:45:03 -03:00
0b5b93053d
shader_ir/other: Implement S2R InvocationId
2019-12-09 23:52:28 -03:00
9ad6327fbd
shader: Keep track of shaders using warp instructions
2019-12-09 23:40:41 -03:00
6233b1db08
shader_ir/memory: Implement patch stores
2019-12-09 23:25:21 -03:00
e36814d6d5
Merge pull request #3109 from FernandoS27/new-instr
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Implement FLO & TXD Instructions on GPU Shaders
2019-12-06 18:18:16 -05:00
dc9961f341
shader/texture: Handle TLDS texture type mismatches
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Some games like "Fire Emblem: Three Houses" bind 2D textures to offsets
used by instructions of 1D textures. To handle the discrepancy this
commit uses the the texture type from the binding and modifies the
emitted code IR to build a valid backend expression.
E.g.: Bound texture is 2D and instruction is 1D, the emitted IR samples
a 2D texture in the coordinate ivec2(X, 0).
2019-11-22 21:28:47 -03:00
32c1bc6a67
shader/texture: Deduce texture buffers from locker
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Instead of specializing shaders to separate texture buffers from 1D
textures, use the locker to deduce them while they are being decoded.
2019-11-22 21:28:47 -03:00
24f4198cee
shader/other: Reduce DEPBAR log severity
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While DEPBAR is stubbed it doesn't change anything from our end. Shading
languages handle what this instruction does implicitly. We are not
getting anything out fo this log except noise.
2019-11-19 21:26:40 -03:00
c8473f399e
Shader_IR: Address Feedback
2019-11-18 07:34:34 -04:00
cd0f5dfc17
Shader_IR: Implement TXD instruction.
2019-11-14 11:15:27 -04:00
f3d1b370aa
Shader_IR: Implement FLO instruction.
2019-11-14 11:15:27 -04:00
56e237d1f9
shader_ir/warp: Implement FSWZADD
2019-11-07 20:08:41 -03:00
08b2b1080a
gl_shader_decompiler: Reimplement shuffles with platform agnostic intrinsics
2019-11-07 20:08:41 -03:00
39c66abd91
shader/decode: Reduce severity of arithmetic rounding warnings
2019-11-07 01:43:38 -03:00
c4374d0d41
shader/arithmetic: Reduce RRO stub severity
2019-11-07 01:43:38 -03:00
35d40b74b3
shader/texture: Remove NODEP warnings
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These warnings don't offer meaningful information while decoding
shaders. Remove them.
2019-11-07 01:43:38 -03:00
654b77d2ec
Merge pull request #3039 from ReinUsesLisp/cleanup-samplers
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shader/node: Unpack bindless texture encoding
2019-11-06 04:54:11 +00:00
23cabc98db
Shader_IR: Fix regression on TLD4
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Originally on the last commit I thought TLD4 acted the same as TLD4S and
didn't have a mask. It actually does have a component mask. This commit
corrects that.
2019-10-30 21:14:57 -04:00
9293c3a0f2
Shader_IR: Fix TLD4 and add Bindless Variant.
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This commit fixes an issue where not all 4 results of tld4 were being
written, the color component was defaulted to red, among other things.
It also implements the bindless variant.
2019-10-30 12:02:03 -04:00
a993df1ee2
shader/node: Unpack bindless texture encoding
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Bindless textures were using u64 to pack the buffer and offset from
where they come from. Drop this in favor of separated entries in the
struct.
Remove the usage of std::set in favor of std::list (it's not std::vector
to avoid reference invalidations) for samplers and images.
2019-10-29 20:53:48 -03:00
26f3e18c5c
Merge pull request #2976 from FernandoS27/cache-fast-brx-rebased
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Implement Fast BRX, fix TXQ and addapt the Shader Cache for it
2019-10-26 16:56:13 -03:00
be856a38d6
Shader_IR: Address Feedback.
2019-10-26 15:38:30 -04:00
d52598173d
Merge pull request #3013 from FernandoS27/tld4s-fix
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Shader_Ir: Fix TLD4S from using a component mask.
2019-10-25 20:06:26 -03:00
33fcec3502
Shader_IR: allow lookup of texture samplers within the shader_ir for instructions that don't provide it
2019-10-25 09:01:30 -04:00
1f5401c89c
video_core/shader: Resolve instances of variable shadowing
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Silences a few -Wshadow warnings.
2019-10-23 23:00:31 -04:00
1509d2ffbd
Shader_Ir: Fix TLD4S from using a component mask.
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TLD4S always outputs 4 values, the previous code checked a component
mask and omitted those values that weren't part of it. This commit
corrects that and makes sure all 4 values are set.
2019-10-22 10:59:07 -04:00
1ea07954fb
shader_ir/memory: Ignore global memory when tracking fails
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Ignore global memory operations instead of invoking undefined behaviour
when constant buffer tracking fails and we are blasting through asserts,
ignore the operation.
In the case of LDG this means filling the destination registers with
zeroes; for STG this means ignore the instruction as a whole.
The default behaviour is still to abort execution on failure.
2019-10-22 02:49:17 -03:00
3d0f357307
shader/half_set_predicate: Fix HSETP2 for constant buffers
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HSETP2 when used with a constant buffer parses the second operand type
as F32. This is not configurable.
2019-10-07 14:49:47 -03:00
632c9e4ee3
shader/half_set_predicate: Reduce DEBUG_ASSERT to LOG_DEBUG
2019-10-07 14:48:58 -03:00
376f1a4432
Merge pull request #2869 from ReinUsesLisp/suld
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shader/image: Implement SULD and fix SUATOM
2019-09-23 21:47:03 -04:00
9286976948
Merge pull request #2878 from FernandoS27/icmp
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shader_ir: Implement ICMP
2019-09-21 18:06:07 -03:00
44000971e2
gl_shader_decompiler: Use uint for images and fix SUATOM
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In the process remove implementation of SUATOM.MIN and SUATOM.MAX as
these require a distinction between U32 and S32. These have to be
implemented with imageCompSwap loop.
2019-09-21 17:33:52 -03:00
675f23aedc
shader/image: Implement SULD and remove irrelevant code
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* Implement SULD as float.
* Remove conditional declaration of GL_ARB_shader_viewport_layer_array.
2019-09-21 17:32:48 -03:00
527b841c15
Shader_IR: ICMP corrections and fixes
2019-09-21 14:28:03 -04:00
88d857499b
Merge pull request #2855 from ReinUsesLisp/shfl
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shader_ir/warp: Implement SHFL for Nvidia devices
2019-09-20 17:10:42 -04:00
4b81d19a1a
Shader_IR: Implement ICMP.
2019-09-19 20:56:29 -04:00
b31880dc5e
Merge pull request #2784 from ReinUsesLisp/smem
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shader_ir: Implement shared memory
2019-09-18 16:26:05 -04:00
0526bf1895
shader_ir/warp: Implement SHFL
2019-09-17 17:44:07 -03:00
36abf67e79
shader/image: Implement SUATOM and fix SUST
2019-09-10 20:22:31 -03:00
34b2c60f95
Merge pull request #2823 from ReinUsesLisp/shr-clamp
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shader/shift: Implement SHR wrapped and clamped variants
2019-09-10 11:56:17 -04:00
1f43e5296f
gl_shader_decompiler: Keep track of written images and mark them as modified
2019-09-05 23:26:05 -03:00
4de04eba39
shader_ir: Implement LD_S
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Loads from shared memory.
2019-09-05 01:38:37 -03:00
f17415d431
shader_ir: Implement ST_S
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This instruction writes to a memory buffer shared with threads within
the same work group. It is known as "shared" memory in GLSL.
2019-09-05 01:38:37 -03:00
77ef4fa907
shader/shift: Implement SHR wrapped and clamped variants
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Nvidia defaults to wrapped shifts, but this is undefined behaviour on
OpenGL's spec. Explicitly mask/clamp according to what the guest shader
requires.
2019-09-04 01:55:24 -03:00
dfae2d141a
half_set_predicate: Fix predicate assignments
2019-09-04 01:54:23 -03:00
81fbc5370d
Merge pull request #2812 from ReinUsesLisp/f2i-selector
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shader_ir/conversion: Implement F2I and F2F F16 selector
2019-09-03 22:35:33 -04:00
d4f33b822b
Merge pull request #2811 from ReinUsesLisp/fsetp-fix
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float_set_predicate: Add missing negation bit for the second operand
2019-09-03 22:34:34 -04:00
4d4f9cc104
video_core: Silent miscellaneous warnings ( #2820 )
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* texture_cache/surface_params: Remove unused local variable
* rasterizer_interface: Add missing documentation commentary
* maxwell_dma: Remove unused rasterizer reference
* video_core/gpu: Sort member declaration order to silent -Wreorder warning
* fermi_2d: Remove unused MemoryManager reference
* video_core: Silent unused variable warnings
* buffer_cache: Silent -Wreorder warnings
* kepler_memory: Remove unused MemoryManager reference
* gl_texture_cache: Add missing override
* buffer_cache: Add missing include
* shader/decode: Remove unused variables
2019-08-30 14:08:00 -04:00
